AXI4 Slave Interface Features - 4.2 English

Zynq 7000 SoC and 7 Series Devices Memory Interface Solutions LogiCORE IP Data Sheet (DS176)

Document ID
DS176
Release Date
2024-05-30
Version
4.2 English

These features are optional and selectable using the MIG GUI:

  • AMBA┬« AXI4 slave-compliant memory-mapped interface
  • AXI4-Lite interface support for ECC control and status registers
  • 1:1 clock rate to the controller
  • AXI4 interface data widths can be 64, 128, 256, or 512 bits to correspond with memory data widths of 8, 16, 32, 64, or 72 bits (72 bits is supported when 64 bits of data and 8 bits of ECC is used)
  • Parameterized address width support
  • Support for incremental (INCR) burst up to 256 data beats
  • WRAP burst support
  • Multicontroller support for up to eight DDR3 SDRAM controllers