The AMD Versal™ adaptive SoC processing system (PS) verification intellectual property (VIP) supports the functional simulation of Versal adaptive SoC applications. It is targeted to enable the functional verification of programmable logic (PL) by mimicking the PS-PL interfaces and OCM memories of PS logic. This VIP is delivered as a package of System Verilog modules. VIP operation is controlled by using a sequence of System Verilog tasks.