- Cache coherency is not supported.
- Exclusive Access (AxLOCK) is not supported.
- Bufferability (AxCACHE) is not supported.
- AxREGION is not supported (SmartConnect inside the VIP does not support AxREGION).
- Latency Modeling for OCM/REG is not supported.
- CHI/CXS/PIPE are not modeled.
- Interconnect arbitration is not modeled as per the RTL.
- Low power modeling is not supported.
- AXI4 user signals cannot be accessed. If accessed, the behavior is undefined.