- Address-based routing and the address map is the same as PS Wizard.
- Design supports multi-clocking.
- Unused PS11 VIP input clocks must be driven with a free-running clock as shown in the example.
The table shows the PS11 VIP mapping input clocks at the Wizard level and PS11 VIP level.
| Top-Level Port Name | Internal Port Name for Driving |
|---|---|
| fpd_axi_pl_aclk | MAXIGP0ACLK |
| lpd_axi_pl_aclk | MAXIGP2ACLK |
| pl_axi_fpd0_aclk | SACE5LGP0WCLK |
| pl_axi_fpd1_aclk | SACE5LGP1WCLK |
| pl_axi_fpd2_aclk | SACE5LGP2WCLK |
| pl_axi_fpd3_aclk | SACE5LGP3WCLK |
| pl_acp_apu_aclk | SAXIACPCLK |
| pl_axi_lpd_aclk | SAXIGP4WCLK |
- All the PS11_VIP AXI interface widths are static (that is, Address and Data widths must not be changed through CIPS GUI). If you try to change the widths the behavior is undefined.
- Currently, PL port widths programming is supported through API
call
select_pl_datawidth. - Narrow transfers are supported for 32/64-bit transfers.
- AXI ID is supported.
- PS11 VIP does not handle any configuration information passed through GUI, except enable and disable of AXI interfaces.
- PS11 VIP is not modeling any AXI path delays.
- 8/16/32-bit width registers are supported.
- ACELITE/ACE5LITE interface supports only AXI4 traffic, all sideband signals are ignored.
- ACP interface supports limited AXI4 features.
- For ACP, AxSIZE is tied to 4 (128-bit).
- AxBURST = 1 (only INCR is supported).
- PL clock/PL reset/PS-PL/PL-PS interrupts can be handled through APIs hooks.