The following shows the PS11 VIP example test case, RPUA_API, is
accessing the OCM0 memory.
`timescale 1ns / 1ps
module tb_top( );
reg tb_ACLK;
reg[1:0] resp;
reg[127:0] read_data;
// Test bench clock generation
initial
begin
tb_ACLK = 1'b0;
end
always #5ns tb_ACLK = !tb_ACLK;
// Test scenario
initial
begin
// Providing the clock to PS11 WIZARD PS VIP
tb_top.DUT.design_1_i.ps11_wizard_0.inst.ps11_l_0.inst.PS11_VIP_inst.inst.ps11_vip_gen_clock(100);
//// Driving the ps11_vip input clocks (Undriven input clocks through GUI must be driven as follows)
force tb_top.DUT.design_1_i.ps11_wizard_0.inst.ps11_l_0.inst.PS11_VIP_inst.inst.fpd_axi_pl_aclk = tb_ACLK;
force tb_top.DUT.design_1_i.ps11_wizard_0.inst.ps11_l_0.inst.PS11_VIP_inst.inst.lpd_axi_pl_aclk = tb_ACLK;
force tb_top.DUT.design_1_i.ps11_wizard_0.inst.ps11_l_0.inst.PS11_VIP_inst.inst.pl_axi_fpd0_aclk = tb_ACLK;
force tb_top.DUT.design_1_i.ps11_wizard_0.inst.ps11_l_0.inst.PS11_VIP_inst.inst.pl_axi_fpd1_aclk = tb_ACLK;
force tb_top.DUT.design_1_i.ps11_wizard_0.inst.ps11_1_0.inst.PS11_VIP_inst.inst.pl_axi_fpd2_aclk = tb_ACLK;
force tb_top.DUT.design_1_i.ps11_wizard_0.inst.ps11_l_0.inst.PS11_VIP_inst.inst.pl_axi_fpd3_aclk = tb_ACLK;
force tb_top.DUT.design_1_i.ps11_wizard_0.inst.ps11_l_0.inst.PS11_VIP_inst.inst.pl_acp_apu_aclk = tb_ACLK;
force tb_top.DUT.design_1_i.ps11_wizard_0.inst.ps11_l_0.inst.PS11_VIP_inst.inst.pl_axi_lpd_aclk = tb_ACLK;
// Applying reset to PS11 VIP, reset should be applied minimum of 16 clock cycles of the slowest clock of PS11_VIP)
tb_top.DUT.design_1_i.ps11_vip_0.inst.por_reset(0);
repeat(20)@(posedge tb_ACLK);
tb_top.DUT.design_1_i.ps11_vip_0.inst.por_reset(1);
fork
begin
//write to OCM memory
tb_top.DUT.design_1_i.ps11_wizard_0.inst.ps11_l_0.inst.PS11_VIP_inst.inst.write_data("RPUA_API",32'hBBF00000,4, 32'h12345678, resp);
$display ("Write into OCM0 memory");
//read from OCM memory
tb_top.DUT.design_1_i.ps11_vip_0.inst.read_data("RPUA_API",32'hBBF00000,4, read_data, resp);
$display ("read from OCM0 memory");
if(read_data == 128'h12345678) begin
$display ("Test PASSED");
end
else begin
$display ("Test FAILED");
end
$display ("Simulation completed");
$stop;
end
begin // This is watch dog timer, to terminate simulation if it hangs
#5us;
$stop;
end
join_any
end // initial
//// DUT instantiation
design_1_wrapper DUT();
endmodule