Renesas Recovered Clock FPGA Bank Source and Associated XDC Net Name

Renesas Recovered Clock FPGA Bank Source and Associated XDC Net Name - DS1016

Alveo UL3422 Ultra Low Latency Trading Data Sheet (DS1016)

Document ID

DS1016

Release Date

2024-10-14

Revision

1.0 English

The following table provides the FPGA bank source and associated XDC net name of the signals connected from the QSFP-DD and ARF6 expansion port to the clock input pins of the Renesas jitter attenuator. See the UL3422 Early Access Secure Site for support details.

Table 1. QSFP-DD, ARF6, and Bank 65 to Jitter Attenuator Recovered Clock Connections
Renesas Recovered Clock Reference	Source Bank	FPGA Pin	XDC Net Name
CLK0	127	AE37	recov_clk_127_lvds_n
CLK0	127	AE36	recov_clk_127_lvds_p
CLK1	130	N37	recov_clk_130_lvds_n
CLK1	130	N36	recov_clk_130_lvds_p
CLK2	227	AG10	recov_clk_227_lvds_n
CLK2	227	AG11	recov_clk_227_lvds_p
CLK3	229	W10	recov_clk_229_lvds_n
CLK3	229	W11	recov_clk_229_lvds_p
CLK4	65¹	BF19	recov_clk_65_lvds_n
CLK4	65¹	BF20	recov_clk_65_lvds_p
The recovery clock RECOV_CLK65 is internally routed through bank 65 and can be sourced from any of the GTF banks through the FPGA fabric.