Renesas Clock Routing - DS1016

The Renesas jitter attenuator has two primary switch matrices to route input clocks to the DPLL array and to the output clock pins. The following figure is a high-level depiction of how this routing is organized.

Figure 1. Clock to DPLL Routing Example

Each of the four predefined configurations includes settings for these switching matrices. The following tables describe the clock input and output routing for the four predefined configurations.

The frequency column for the input clock/DPLL routing corresponds to the frequency of the DPLL’s generated clock to which the device is tuned in order to reduce jitter and generate a stable clock. The frequency column for the output clock/DPLL routing corresponds to the expected output clock frequency of the corresponding pin.