One pulse per second (1PPS) input and output interfaces, located on the PCIe I/O bracket, provide synchronization between external system clock synchronization units. Both 1PPS interfaces are compatible with plug-type SSMB adaptors and cables (such as Pasternack PE3139LF series cables). The 1PPS input is terminated with a 50Ω load. The following table provides the XDC net name and associated pin assignment.
| Net Name | Pin Assignment |
|---|---|
| PPS_IN_FPGA | BF14 |
| PPS_OUT_FPGA | BF15 |