Jitter Attenuator - DS1016

Alveo UL3422 Ultra Low Latency Trading Data Sheet (DS1016)
Document ID
DS1016
Release Date
2024-10-14
Revision
1.0 English

The jitter attenuator logic for the QSFP-DD and ARF6 ports consists of various temperature-controlled crystal oscillators and ultra-low jitter components that provide exceptional jitter attenuation and clock fidelity. The Resesas RC38612 jitter attenuator device is the heart of the jitter attenuation logic. It has the ability to program different configurations by routing input clocks through an array of internal digitally controlled oscillators (DCOs) or digital phase locked loops (DPLLs) before routing to a set of output pins.

The following figure shows the high-level connections between the QSFP-DD and ARF6 expansion port GTFs, and the Renesas jitter attenuator. The jitter attenuator can select one of five recovered clock inputs:

  • Two recovered clocks are dedicated routes from QSFP-DD GTF ports.
  • Two recovered clocks are dedicated routes from the ARF6 ports.
  • One recovered clock is indirectly routed from the GTF banks via FPGA bank 65.
Figure 1. QSFP-DD and Expansion Port Jitter Attenuation Connections

The jitter attenuator generates twelve attenuated output clocks.

  • Four of the generated clocks are routed to the GTF banks associated with the QSFP-DD ports.
  • Four generated clocks are routed to the GTF banks associated with the ARF6 ports.
  • Two generated clocks are routed to GTF banks 129 and 226 allowing additional clock sources adjacent to the QSFP-DD and ARF6 ports.
  • The two remaining generated clocks are routed to HDIO pins in bank 65 for use in the FPGA fabric.

See FPGA Bank Destination and Associated XDC Net Name for clock to bank mapping.

Designers should closely examine the Renesas RC38612 Datasheet to fully understand how to configure and use the device. The jitter attenuator is programmed via an I2C bus to configure its features such as selecting input clocks, configuring PLLs, and phase aligning output clocks with the internal FPGA reference clocks. The output clocks can be flexibly assigned to specific PLLs to create clocking subgroups. While the jitter attenuator has some flexibility in routing outputs to internal DCO/DPLLs, it does not allow all twelve outputs to be connected to the same DCO/DPLL.

Important: The four external recovery clocks from banks 127 (RECOV_CLK127), 130 (RECOV_CLK130), 227 (RECOV_CLK227), and 229 (RECOV_CLK229) are hardwired to the jitter attenuator. The recovery clock RECOV_CLK_65 is internally routed through bank 65 and can be sourced from any of the GTF banks through the FPGA fabric.