FPGA Configuration Memory - DS1016

Alveo UL3422 Ultra Low Latency Trading Data Sheet (DS1016)

Document ID
DS1016
Release Date
2024-10-14
Revision
1.0 English

The card is populated with 2 Gb QSPI flash memory, which provides space to store up to four maximum-sized FPGA bitstreams. The following table details the QSPI component.

Table 1. QSPI Device Details
Parameter Description
Manufacturer Micron
Part number MT25QU02GCBB8E12
Details

Speed 75 MHz

Density 2 Gb (256M x 8)

Two FPGA configuration modes are supported:

  • Master SPI x4
  • JTAG (over Micro-USB or ADK2 debug connector)

The FPGA bank 0 mode pins are hardwired to master SPI mode M[2:0] = 001 with pull-up/pull-down resistors. At power up, the FPGA is configured by the Quad SPI NOR flash device using the primary serial configuration mode.

Table 2. Configuration Modes
Configuration Mode M[2:0] Bus Width CCLK Direction
Master SPI 001 x1, x2, x4 FPGA output
JTAG Not applicable – JTAG overrides x1 Not applicable