FPGA Bank I/O Mapping

FPGA Bank I/O Mapping - DS1016

Alveo UL3422 Ultra Low Latency Trading Data Sheet (DS1016)

Document ID

DS1016

Release Date

2024-10-14

Revision

1.0 English

The following figure and associated table gives the FPGA bank I/O allocation. This includes additional details for assigned function and VCCO allocation. Both HDIO (high density I/O) and HPIO (high performance I/O) banks are used. Allocation of bank type is dependent on the required function (i.e., memory interface or UART). Bank 0 is a dedicated bank allocated for JTAG and configuration QSPI interface. It is not detailed in the table.

Figure 1. FPGA Bank Allocation

Table 1. FPGA Bank Allocation
FPGA Bank	Bank Type	Function(s)	VCCO
65	HPIO	RX recovered clocks EMCCLK	1.8
66 - 68	HPIO	DDR4 Controller	1.2
88	HDIO	Three UARTs QSFP-DD LEDs PPS IN / OUT	3.3
93	HDIO	Expansion Sideband 1 & 2 QSFP-DD Sideband	3.3
127 - 128	GTF	QSFP-DD 1 TX / RX 1-4 assigned to bank 127 TX / RX 5-8 assigned to bank 128	N/A
130- 131	GTF	QSFP-DD 2 TX / RX 1-4 assigned to bank 130 TX / RX 5-8 assigned to bank 131	N/A
224 - 225	GTY	PCIe x8 to Edge Connector PCIe Lane 3-0 on bank 225 PCIe Lane 7-4 on bank 224 Upper 8 lanes of PCIe x16 connector are not connected.	N/A
227 - 228	GTF	ARF6 1 Expansion Connector TX / RX 1-4 assigned to bank 227 TX / RX 5-8 assigned to bank 228	N/A
229 - 230	GTF	ARF6 2 Expansion Connector TX / RX 1-4 assigned to bank 229 TX / RX 5-8 assigned to bank 230	N/A