FPGA Bank Destination and Associated XDC Net Name

FPGA Bank Destination and Associated XDC Net Name - DS1016

Alveo UL3422 Ultra Low Latency Trading Data Sheet (DS1016)

Document ID

DS1016

Release Date

2024-10-14

Revision

1.0 English

The following tables provide the FPGA bank destination and associated XDC net name of the signals connected from the Renesas jitter attenuator's clock outputs to the QSFP-DD, ARF6 expansion port, and Bank 65 clock reference pins. See the UL3422 Early Access Secure Site for support details.

Table 1. Jitter Attenuator to QSFP-DD Port SYNC-E Clock Connection
Renesas Recovered Clock Reference	Source Bank	FPGA Pin	XDC Net Name
Q4	127	AG37	synce_clk_127_lvds_n
Q4	127	AG36	synce_clk_127_lvds_p
Q5	128	AC37	synce_clk_128_lvds_n
Q5	128	AC36	synce_clk_128_lvds_p
Q6	129	W37	synce_clk_129_lvds_n
Q6	129	W36	synce_clk_129_lvds_p
Q7	130	R37	synce_clk_130_lvds_n
Q7	130	R36	synce_clk_130_lvds_p
Q11	131	L37	synce_clk_131_lvds_n
Q11	131	L36	synce_clk_131_lvds_p

Table 2. Jitter Attenuator to ARF6 Expansion Port SYNC-E Clock Connections
Renesas Recovered Clock Reference	Source Bank	FPGA Pin	XDC Net Name
Q1	226	AN10	synce_clk_226_lvds_n
Q1	226	AN11	synce_clk_226_lvds_p
Q2	227	AJ10	synce_clk_227_lvds_n
Q2	227	AJ11	synce_clk_227_lvds_p
Q3	228	AE10	synce_clk_228_lvds_n
Q3	228	AE11	synce_clk_228_lvds_p
Q9	229	AA10	synce_clk_229_lvds_n
Q9	229	AA11	synce_clk_229_lvds_p
Q10	230	U10	synce_clk_230_lvds_n
Q10	230	U11	synce_clk_230_lvds_p

Table 3. Jitter Attenuator to Bank 65 HDIO Connections
Renesas Recovered Clock Reference	Source Bank	FPGA Pin	XDC Net Name
Q0	65	BB20	synce_clk_65_2_lvds_n
Q0	65	BA20	synce_clk_65_2_lvds_p
Q8	65	BA17	synce_clk_65_1_lvds_n
Q8	65	AY17	synce_clk_65_1_lvds_p