The card provides the following reference clocks:
- PCIe® reference clocks
- Memory controller (DDR4) reference clocks
- User reference clock
- Ethernet reference clocks
The following high-level clock tree diagram shows the advanced clocking and jitter attenuator logic. See the following section for additional details.
Figure 1.
UL3422 Clocking Tree
The card uses the Renesas RC21008AQ clock generator to provide reference clocks for PCIe, user reference, as well as a DDR4 memory controller. The following table lists the Renesas clock output reference and frequency, along with the FPGA destination bank and XDC net names. Renesas clock output references that are not provided in the table are not connected.
| Renesas RC21008AQ Clock Output Reference | Frequency (MHz) | Destination FPGA Bank | Block Reference Clock | XDC Net Name |
|---|---|---|---|---|
| OUT1 | 100 | 225 | PCIe |
clk_pcie_lvds_100_n clk_pcie_lvds_100_p |
| OUT2 | 300 | 65 | User |
clk_sys_lvds_300_n clk_sys_lvds_300_p |
| OUT3 | 300 | 66 | DDR4 memory controller |
clk_ddr_lvds_300_n clk_ddr_lvds_300_p |