ADK2 and USB Port Precedence - DS1016

Alveo UL3422 Ultra Low Latency Trading Data Sheet (DS1016)

Document ID
DS1016
Release Date
2024-10-14
Revision
1.0 English

The ADK2 and micro USB UART and JTAG interfaces share internal logic to access the various protocols. The following figure shows the shared internal logic. The MUX is controlled by DMB_PRSNT_B, which is internally set when the ADK2 debug module is connected.

Figure 1. USB and ADK2 Debug Connector Shared Logic

Access control is granted based on the following precedence rules:

  • If the ADK2 debug module is connected, it has control of the shared ports.
  • If ADK2 debug module is not connected, USB has control of the shared ports.