Block Diagram

Alveo U45N Data Center Accelerator Card Data Sheet (DS1014)

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1.0 English

The high-level block diagram for the Alveo U45N accelerator card is given in the following figure.

Figure 1. Alveo U45N Accelerator Card Block Diagram

The XCU26 is based on the 16 nm AMD UltraScaleā„¢ architecture. The programmable logic (PL) region is connected to two QSFP28 cages. The XCU26 also has two 4 GB x72 of DDR4 memory component interfaces and a PCIe CEM 3.0 compliant x16 edge-finger interface.

The XCU26 is connected to an NXP Layerscape LX2162A Arm processor through a PCIe 3.0 compliant x8 interface. The LX2162A supports 16 Cortex-A72 cores, a 46 Gb/s security engine and an 88 Gb/s data compression engine. For system applications, the LX2162A has a dedicated DDR4 memory interface with 4 GB x72 DDR4, a dedicated 16 GB eMMC NAND, and a 512 Mb OSPI NOR flash. The Arm processor on the U45N accelerator card helps to increase the server CPU efficiency and lower total costs by offloading workloads from the host. For more information on utilizing the LX2162A, contact AMD sales representative.

Figure 2. XCU26 Communication Processor Floorplan