Enabling or disabling the individual QSFP56 power domains is achieved by configuring a TCA6408APWR I/O expander that drives the power enable signals.
- Ports 0 to 3 must be configured as outputs. They control the power enables for each domain.
- Ports 4 to 7 must be configured as inputs. They return the power good status of each domain.
Note: While the card can operate without either AUX power
connected, power to the QSFP cages, DDR, and DIMMs requires at least AUX power
connector 1 to be connected.
The following table provides the TCA6408APWR I/O expander bit settings and function.
| Bit | Function | Direction | Signal |
|---|---|---|---|
| 0 | QSFP56 1 Power Enable | Output | QSFP EN |
| 1 | QSFP56 2 Power Enable | Output | QSFP EN |
| 2 | QSFP56 3 Power Enable | Output | QSFP EN |
| 3 | QSFP56 4 Power Enable | Output | QSFP EN |
| 4 | QSFP56 1 Power Good | Input | QSFP PG |
| 5 | QSFP56 2 Power Good | Input | QSFP PG |
| 6 | QSFP56 3 Power Good | Input | QSFP PG |
| 7 | QSFP56 4 Power Good | Input | QSFP PG |
The following table provides the three steps necessary to configure the I/O expander, enable the outputs, and read back the power good values for verification.
| Function | I2C | Sequence |
|---|---|---|
| Set power enable pins | 0x21, 0x01, 0x0F | Programs output value register. |
| Enable output mode for even numbered pin | 0x21, 0x03, 0xF0 | Programs output config register (0 = output, 1 = input) |
| Read power good status | 0x21, 0x00, 0xFF (expected read data) | Reads input value register |