I2C Memory Map

Alveo V80 Data Center Accelerator Cards Data Sheet (DS1013)
Document ID
DS1013
Release Date
2024-05-08
Revision
1.0 English

The following table provides the I2C base address memory map for accessible devices. There are two I2C interfaces, I2C_QSFP and I2C_MAIN, and an SMBUS. The I2C interfaces are accessible from the adaptive SoC (shown below). The table groups these registers accordingly. For specific I2C register details, see the manufacturer's respective device datasheet.

Table 1. I2C Base Address Memory Map
Register Name

8-bit

(HEX)

7-bit

(HEX)

 Description Manufacturer/Device Comment
Address
Accessible from SMBUS Interface
FRU_EEPROM 0xA0 0X50 64 Kb EEPROM ST M24C64 FRU EEPROM (See Alveo Data Center Accelerator Cards FRU Data Specification)
Accessible from I2C_MAIN Adaptive SoC Interface
Clock generator 0x12 0x09 Clock generator component SiTime SiT95141 Clock generator status and control registers
TempSensor_IO_Bracket 0X34 0x1A Temperature Sensor Onsemi CAT34TS02VP2GT4C I/O bracket temperature sensor
IO_Expander 0X40 0X20 I2C I/O Expander TI TCA6416AR GPIO Expander
PWR_MON1 0X80 0X40 Current/voltage monitor TI INA3221

Read voltage and current for:

  • 12V_PEX
  • 3V3_PEX
  • 3V3_QSFP
PWR_MON2 0X82 0X41 Current/voltage monitor TI INA3221

Read voltage and current for:

  • 1V2_DIMM
  • 12V_AUX1
  • 12V_AUX2
MFG EEPROM 0XA4 0x52 MFG EEPROM Onsemi CAT34TS02VP2GT4C  
PCIe_ClkBuf 0XD8 0x6C PCIe Clock Buffer Renesas RC19013A Access clock buffer status.
PWR_CONT1 0XC0 0X60 6-Phase PWM Controller 1 Renesas ISL68224IRAZ Read voltage and current and other status for core voltage VCCINT.
PWR_CONT2 0XC2 0X61 6-Phase PWM Controller 2 Renesas ISL68224IRAZ Read voltage and current and other status for HBM, CPM5, and GTXAVTT.
QSFP56 - Accessible from the Adaptive SoC I2C_QSFP Interface
QSFP56_EN_PG 0X42 0X21 I2C I/O Expander TI TCA6408APWR QSFP56 1–4 Enable and Power Good. Access directly off the I2C_QSFP interface.
QSFP56 1/2 Mux 0XE0 0X70 Four-channel I2C Mux NXP PCA9545ABS Mux between QSFP56 1/2
QSFP56 3/4 Mux 0XE2 0X71 Four-channel I2C Mux NXP PCA9545ABS Mux between QSFP56 3/4
QSFP56_IO_EXP 0x40 0x20 I2C I/O Expander TI TCA6408APWR QSFP56 1–4 Sideband signal access. Access indirectly via QSFP56 Mux.
QSFP56_REG_ACCESS 0XA0/0XA4 0X50/0X52 Pass-through to QSFP56 module N/A QSFP56 1–4 access to QSFP56 I2C registers. Access indirectly via QSFP56 Mux. Address is QSFP56 module dependent. See module data sheet.
DIMM and PCIe I2C Expansion 0XE4 0X72 Four-channel I2C Mux NXP PCA9545ABS I2C interface for
  • MCIO expansion ports
  • SPD DIMM (EEPROM 0x50 7-bit; Temp Sensor 0x18 7-bit)

The following figure shows the devices accessible via the I2C interfaces, as well as those accessible through SMBUS, UART, and JTAG.

Figure 1. I2C and JTAG Accessible Devices