The following high-level clock tree diagram shows the advanced clocking logic.
It includes a PCIe Gen5 clock buffer (Renesas RC19013A) to distribute the 100 MHz PCIe Gen5 clock, originating from the PCIe edge connector. The following table lists various output clocks from the buffer.
| Clock Output Reference | Frequency | Destination Adaptive SoC Bank | Block Reference Clock | XDC Net Name |
|---|---|---|---|---|
| OUT0 | LVDS 100 MHz | GTYP105 | Host PCIe Gen5 2x8 | PCIE_105_REFCLK0_N PCIE_105_REFCLK0_P |
| OUT1 | LVDS 100 MHz | GTYP104 | PCIE_104_REFCLK0_N PCIE_104_REFCLK0_P |
|
| OUT2 | LVDS 100 MHz | GTYP103 | PCIE_103_REFCLK0_N PCIE_103_REFCLK0_P |
|
| OUT3 | LVDS 100 MHz | GTYP102 | PCIE_102_REFCLK0_N PCIE_102_REFCLK0_P |
|
| OUT4 | NOT CONNECTED | |||
| OUT5 | NOT CONNECTED | |||
| OUT6 | LVDS 100 MHz | GTYP200 | Expansion Ports 4x PCIe Gen5 x4 | MCIO_200_REFCLK0_N MCIO_200_REFCLK0_P |
| OUT7 | LVDS 100 MHz | GTYP213 | MCIO_213_REFCLK0_N MCIO_213_REFCLK0_P |
|
| OUT8 | LVDS 100 MHz | GTYP214 |
MCIO_214_REFCLK0_N MCIO_214_REFCLK0_P |
|
| OUT9 | LVDS 100 MHz | GTYP218 |
MCIO_218_REFCLK0_N MCIO_218_REFCLK0_P |
|
| OUT10 | HCSL 100 MHz | MCIO J12 (MCIO Port 2) |
MCIO_C_P2_REFCLK_C_N MCIO_C_P2_REFCLK_C_P |
|
| OUT11 | HCSL 100 MHz | MCIO J11 (MCIO Port 3) | MCIO_C_P3_REFCLK_C_N MCIO_C_P3_REFCLK_C_P |
|
| OUT12 | HCSL 100 MHz | MCIO J10 (MCIO Port 1) |
MCIO_C_P1_REFCLK_C_N MCIO_C_P1_REFCLK_C_P |
|
| OUT13 | NOT CONNECTED | |||
| OUT14 | NOT CONNECTED | |||
In addition, it also includes a clock generator (SiTime SiT95141) which provides reference clocks for the various blocks detailed in the following table.
| SiTime SiT95141 | Frequency | Destination Adaptive SoC Bank | Block Reference Clock | XDC Net Name |
|---|---|---|---|---|
| OUT4 | LVDS 200 MHz | 800 | HBM |
HBM_800_REFCLK_N HBM_800_REFCLK_P |
| OUT5 | LVDS 200 MHz | 801 | HBM |
HBM_801_REFCLK_N HBM_801_REFCLK_P |
| OUT6 | LVDS 200 MHz | 701 | DDR4 memory controller |
sys_clk0_0_clk_n sys_clk0_0_clk_p |
| OUT7 | LVDS 200 MHz | 703 | DDR4 DIMM |
sys_clk0_1_clk_n sys_clk0_1_clk_p |
| OUT0 | 322.265 MHz | GTM111 | QSFP56 |
QSFP_GTM111_REFCLK_N QSFP_GTM111_REFCLK_P |
| OUT1 | 322.265 MHz | GTM209 | QSFP56 |
QSFP_GTM209_REFCLK_N QSFP_GTM209_REFCLK_P |
Finally, there are two on-board LVCMOS18 33.333333 MHz reference clocks sourced by the Onsemi NB3V1102CMTTBG clock buffer. The clock is sourced by a 33.33333 MHz oscillator. Details are given in the following table.
| Onsemi NB3V1102CMTTBG Clock Output Reference |
Frequency | Destination Adaptive SoC Bank | Block Reference Clock | XDC Net Name |
|---|---|---|---|---|
| Q0 | LVCMOS18 33.333333 MHz | 503 | Reference Clock | REF_CLK0 |
| Q1 | LVCMOS18 33.333333 MHz | 503 | Reference Clock | REF_CLK1 |