Adaptive SoC I/O Bank Mapping

Alveo V80 Data Center Accelerator Cards Data Sheet (DS1013)
Document ID
DS1013
Release Date
2024-05-08
Revision
1.0 English

The following table provides the adaptive SoC bank I/O allocation, associated function, and bank type. Allocation of bank type is dependent on the required function.

Table 1. Adaptive SoC Bank Allocation
Adaptive SoC Bank Bank Type Function(s)
105 – 102 GTYP PCIe x16 to Edge Connector:
  • PCIe lane 3–0 on bank 105
  • PCIe lane 7–4 on bank 104
  • PCIe lane 11–8 on bank 103
  • PCIe lane 15–12 on bank 102
111 GTM QSFP56 4
112 GTM QSFP56 3
210 GTM QSFP56 2
209 GTM QSFP56 1
213 – 214 GTYP MCIO_2 (x8):
  • TX/RX 1–4 assigned to bank 213
  • TX/RX 5–8 assigned to bank 214
200 GTYP MCIO_1 (x4)
218 GTYP MCIO_3 (x4)
700 – 702 XPIO DDR4 discrete memory
703 – 705 XPIO DDR4 DIMM
500, 503 PMC Config, OSPI, and eMMC
501 – 502 PMC/LPD

I2C QSFP sideband signals - Adaptive SoC LPD I2C1 in bank 502 is used as a management bus for QSFP56 ports and expansion connectors:

  • MCIO sideband signals
  • Logging flash

I2C Main - Adaptive SoC LPD I2C0 in bank 502 is used as a management bus for VRMs, input power monitor, clock generator, and MFG EEPROM:

  • LEDs
  • PWRBRK#