Adaptive SoC configuration is supervised by an on-chip platform management controller (PMC). Upon card power-on or reset, the MODE pins (shown in the following table) dictate the primary boot memory device. The card has fixed pin strap to OSPI boot mode (0x8). JTAG mode (0x0) can always be selected by accessing the MODE register through JTAG chain. See the Xilinx Design Constraints (XDC) file for more details.
| Mode Pin | Default Value | Adaptive SoC Pin |
|---|---|---|
| 0 | 0 | BG2 |
| 1 | 0 | BH2 |
| 2 | 0 | BJ2 |
| 3 | 1 | BK2 |