Vivado Simulator - UG1192

The Vivado simulator is a hardware description language (HDL) event-driven simulator that supports behavioral and timing simulations for:

• VHDL
• Verilog
• SystemVerilog
• Mixed VHDL/Verilog or VHDL/SystemVerilog designs

See Vivado Design Suite User Guide: Logic Simulation (UG900) for more information.