Versal Architecture Specific Architectural Features for Migration - UG1192

AMD Design Conversion for Altera FPGAs and SoCs Methodology Guide (UG1192)

Document ID
UG1192
Release Date
2025-07-15
Revision
3.0.1 English

Versal devices include several unique features and architectural changes that differ from Altera’s Agilex. This section focuses on Versal device features including the platform management controller (PMC), control, interfaces, and processing system (CIPS), network-on-chip (NoC), AI Engines (AIE), and PL-PS connectivity. These features impact how to approach migration from Agilex to Versal devices. The goal is to equip you with the knowledge required to adapt your hardware and software designs for these new capabilities, while ensuring optimal performance and efficiency. For further details on the NoC or AIE features, see Versal Architecture NoC and AI Engines.