The Versal architecture has some notable additions compared to previous generations of FPGA and adaptive SoC devices. It is worth noting these differences because they offer advantages to use in your design. Along with these advantages there are new tools and flows. Understanding the Versal device features is critical to optimal operation of these components and minimal iterations through the design cycle on the way to production.
To get started, there is a Versal Adaptive SoC Design Flow Assistant (in the AMD Technical Imformation Portal) to help guide you through the process of designing with Versal devices.
There are details on the control, interfaces, and processing system (CIPS) and platform management controller (PMC) IP in the Versal Architecture Specific Architectural Features for Migrationsection. CIPS requires use of the Vivado IP integrator, that offers many system-level benefits as described in Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994).