In the UltraScale+ portfolio there are three types of general-purpose transceivers optimized for different usage profiles as shown in the following table.
| Feature | GTH | GTY | GTM |
|---|---|---|---|
| Line rate 1 | 0.5–16.3 Gb/s NRZ | 0.5–32.75 Gb/s NRZ | PAM4: 39.2–58 Gb/s, 20.6–29 Gb/s NRZ: 19.6–29 Gb/s, 10.3–14.5 Gb/s |
| Organization | Quad TX/RX channels | Quad TX/RX channels | Dual TX/RX channels |
| Ring PLL (CPLL) | 1 per TX/RX channel 0.5–12.5 Gb/s |
1 per TX/RX channel 0.5–12.5 Gb/s |
N/A |
| LC PLL (QPLL) | 2 per quad 1.0–16.3 Gb/s |
2 per quad 1.0–32.75 Gb/s |
1 per dual |
| Reference clock sources | 2 input buffers per quad with sharing from 2 quads above or below | 2 input buffers per quad with sharing from 2 quads above or below | 1 input buffer per dual, with sharing from 1 dual north or south 2 |
| Integrated PCS features |
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| Examples usages | Backplane, PCIe, 1G, 2.5G, 5G, 10G Ethernet, SAS, SATA, HDMI | Backplane, PCIe, 10G, 25G, 50G, 100G Ethernet, Interlaken | Backplane, 10G, 25G, 50G, 100G,200G, 400G Ethernet, OIF CEI-56G, CPRI 48G |
| Found in some of these devices: | Artix UltraScale+ FPGAs, Kintex UltraScale+ FPGAs, Virtex UltraScale+ FPGAs, Zynq UltraScale+ MPSoCs | Artix UltraScale+ FPGAs, Kintex UltraScale+ FPGAs, Virtex UltraScale+ FPGAs, Zynq UltraScale+ MPSoCs, Zynq UltraScale+ RFSoCs | Virtex UltraScale+ FPGAs |
| Documentation | UltraScale Architecture GTH Transceivers User Guide (UG576) | UltraScale Architecture GTY Transceivers User Guide (UG578) | Virtex UltraScale+ FPGAs GTM Transceivers User Guide (UG581) |
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UltraScale+ Portfolio's GTH and GTY Transceivers
GTH and GTY transceivers support NRZ modulation and have numerous additional features to support a wide range of protocols and standards. The PCS blocks include the most common data encoding/decoding formats as integrated logic to saves substantial programmable resources.
The transceivers are organized into quad TX/RX SerDes channels with flexible clocking resources that allow any TX or RX channel to have independent frequency selection.
UltraScale+ Portfolio's GTM Transceivers
GTM transceivers support both PAM4 and NRZ modulations. PAM4 increases throughput by using four differential voltage levels to convey 2-bits per symbol period without increasing the channel’s Nyquist frequency. Integrated Reed-Soloman forward error correction increases effective margin in challenging channel loss use cases.
GTM transceivers are organized as a dual with two TX/RX channels sharing a single LC PLL with the implication that both TX/RX channels of the dual operate at the same frequency.
PS-GTR Transceivers
The processing system (PS) of the Zynq UltraScale+ MPSoCs and Zynq UltraScale+ RFSoCs feature the PS-GTR transceiver integrated as a dedicated PS peripheral. This allows the PS to selectively interface to USB, PCIe, SATA, DisplayPort, or Ethernet protocols without consuming programmable resources. For more information about PS-GTR transceivers, refer to the Zynq UltraScale+ Device Technical Reference Manual (UG1085).
GTF Transceiver in the Alveo UL3524
The GTF transceiver in the AMD Alveo™ UL3524 accelerator card is optimized for ultra-low latency applications where every nanosecond matters. It supports 10G and 25G Ethernet speeds.