The FPGA/SoC transceivers are highly customizable. The transceiver parameters must be set correctly to attain the desired characteristics and performance.
- Altera Transceiver Toolkit/AMD IBERT
- Offers a solution for debugging and optimizing FPGA transceivers. This solution includes a customizable debug IP (IBERT) that is integrated into the transceivers. The Vivado serial I/O analyzer tool is used to access the transceiver debug features to take bit-error ratio (BER) measurements on multiple channels, perform 2D eye scans, and adjust transceiver parameters in real-time while your serial I/O channels interact with the rest of the system.
Designed for PMA evaluation and demonstration of transceivers, IBERT also includes data pattern generators and checkers, as well as access to transceivers DRP ports. After IBERT is implemented within the FPGA, the Vivado serial I/O analyzer interacts with the IP and allows you to create links (analogous to a channel on a board) and analyze the margin of the links by running scans and viewing the results graphically.
These AMD user guides and videos provide detailed information about the Vivado serial logic analyzer tool:
- For more information on debugging options in the Vivado Design Suite, see the Vivado Design Suite User Guide: Programming and Debugging (UG908).
- For more information on the customizable integrated bit error ratio tester (IBERT) core for UltraScale+ GTM Transceivers, refer to IBERT for UltraScale GTM Transceivers LogiCORE IP Product Guide (PG342).
- For more information on the customizable integrated bit error ratio tester (IBERT) core for UltraScale+ GTY Transceivers, refer to IBERT for UltraScale GTY Transceivers LogiCORE IP Product Guide (PG196).
- For more information on the customizable integrated bit error ratio tester (IBERT) core for UltraScale+ GTH Transceivers, refer to IBERT for UltraScale GTH Transceivers LogiCORE IP Product Guide (PG173).