As mentioned in the synthesis section, the Vivado Design Suite offers timing estimation and analysis capabilities throughout the entire design flow. Accurate timing constraints are important because timing is evaluated against these constraints, and Vivado tools uses the estimates to guide synthesis optimizations, placement, physical optimizations, and routing.
Although Vivado tools only report timing of the
fully implemented design and the IDE only provides a direct way to load this routed
design in the Implemented Design view, timing can be
analyzed through the entire flow. After opt_design, place_design, post-place
phys_opt_design, and route_design, the design checkpoint (DCP) is automatically
generated and stored. These checkpoints can be loaded from the GUI menu to select
, using the open_checkpoint Tcl command
or when loading Vivado tools from the command prompt
using Vivado
<filename.dcp>.
AMD recommends monitoring and reviewing the timing throughout the flow. This is part of the foundation of the UltraFast Design Methodology: Accurate timing constraints combined with timing closure throughout the flow. Timing regression during every stage can point out specific issues:
- After synthesis or opt_design: Logic delay, CDC constraint or clock topology issues
- After place_design or phys_opt_design: Physical timing issues like insufficient pipelining or fanout
- After route_design: Hold time fixing or routing congestion issues
All details on design closure can be found in the comprehensive UltraFast Design Methodology Guide for FPGAs and SoCs (UG949) for non-Versal devices and the Versal Adaptive SoC System Integration and Validation Methodology Guide (UG1388) for Versal devices. There is also a short summary of the UltraFast design methodology specifically for timing closure in the UltraFast Design Methodology Timing Closure Quick Reference Guide (UG1292). Several reports and tools can be run at each design stage to assist with timing closure analysis:
Design Analysis Report
This report provides all relevant metrics of the critical timing paths and device areas of the design in a convenient table to help identify and analyze problem areas that are subject to timing closure issues and routing congestion.
It can be run either from the GUI menu select or using the report_design_analysis Tcl command. For
more information on this command refer to the
Vivado
Design Suite User Guide: Design Analysis and Closure
Techniques (UG906).
Methodology and DRC Report
These reports check the design against a methodology and design rule checks
(DRC). Review these reports at least one time because they can point out issues with
timing constraints or the netlist. Ideally, the reports are reviewed after the first
compilation and after major design changes. Violations can be waved (create_waver)
if not important. The reports are available in the Vivado IDE or through the report_methodology and report_drc Tcl
commands.
Details on the DRC and the methodology report warnings are in the Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)
QoR Assessment Report
This report assesses the design QoR performance by providing a score, details of the metrics used and relevant methodology checks. It also recommends ML-based implementation strategies and lists challenging timing paths using net/LUT budget and clock skew. Also, objects with DONT_TOUCH properties that prevent physical optimization, and very high fanout logic driven nets are reported.
To generate this report, use the report_qor_assessment Tcl command
or generate it from the menu select .
Details on this QoR assessment report can be found in the Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)
QoR Suggestions Report
This report provides specific suggestions to improve the design's QoR by analyzing the design and offering targeted recommendations. Suggestions include changes to constraints, design structures, and implementation strategies.
To generate this report, use the report_qor_suggestions Tcl command,
or it can be accessed through the Vivado IDE under the menu select .
Further insights and details on interpreting the QoR suggestions report can be found in the Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)
Intelligent Design Runs
Unlike the other tools, the intelligent design runs (IDR) tool fully automates
timing closure. It works in three stages. In the first stage, IDR leverages the
information from report_qor_suggestions and
intelligently applies the suggestions to optimize the netlist. After the design is
fully optimized, it runs the three best implementation strategies based on ML.
If timing still is not met after stage 2, it runs a last-mile timing closure flow (stage 3) where only the failing paths are incrementally placed and routed.
To run this tool, right-click on a design run and select Close Timing using Intelligent Design Runs.
For more information about IDR, see the Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906).