| Concept/Feature | AMD | Altera | Description |
|---|---|---|---|
| Processor subsystem | Processing system (PS) | Hard processor system (HPS) | Integrated ARM-based CPU subsystem |
| Reconfigurable logic | Programmable logic (PL) | FPGA fabric | The programmable/reconfigurable logic portion of the device. |
| Processing subsystem-FPGA interface | PS-PL interfaces | HPS-FPGA bridges | Interfaces between the processor subsystem and PL (fabric). |
| High-speed interfaces | GTH/GTY/GTM transceivers (GTs) | High-speed transceivers | High-speed serial I/O interfaces for protocols like PCIe and Ethernet. |
| Boot/configuration logic | Configuration logic, BootROM, FSBL/PLM, | BootROM, preloader | Logic for booting and initializing the SoC and configuring the FPGA. |
| PL/FPGA configuration file |
Bitstream for FPGAs or Zynq UltraScale+ devices (.bit or .rbf) Bitstream for Versal adaptive SoC (.rnpi or .rcdo) |
SRAM object file (.sof) | File used to configure the FPGA. |
| Handoff files | .xsa | Handoff + .sof | The hardware design output to be used by the software development environment. |
| On-chip memory (PL/FPGA) | Block RAM and UltraRAM | M20K | RAM integrated into the FPGA |
| Distributed memory (PL/FPGA) | DRAM or LUTRAM | MLABs | Logic elements configured as memory |
| On-chip memory (PS/HPS) | On-chip memory (OCM) | On-chip RAM (OCRAM) | Arm processor supporting memory found in the PS/HPS. |
| Embedded debug and trace infrastructure |
CoreSight™
technology JTAG and DAP subsystem |
CoreSight technology debug and trace |
Provide processor debug and performances analysis features |
| Hardware design tools | Vivado Design Suite | Quartus Prime | Design suite for creating FPGA-based systems. |
| Hardened Peripherals | Integrated IP (for example: PCIe) | Embedded peripherals | Pre-implemented, dedicated silicon, IP blocks for functions like PCIe, Ethernet, and memory |
| Design tool for interconnecting IP blocks and processor subsystems |
Vivado IP integrator (part of the Vivado Design Suite) |
Platform designer (used to be called Qsys) | Both tools are used to configure and connect IP blocks. The IP integrator GUI makes it much more convenient to add and connect IP cores. |
| Interconnect (processor/logic) | AMBA® (AXI) interconnect | AXI connect | Multi-layered (All the blocks are connected to each other and to the PL through this interconnect system). |
| Integrated development environment (IDE) | AMD Vitis unified software platform or classic | SoC EDS professional edition + Arm development studio for Altera SoC FPGA edition | Development tools, utility programs, runtime software, application examples |
| Linux development environments | Yocto | Yocto | Environment to build and deploy embedded Linux solutions on processing systems. |
| Boot image/programming image |
Programmable device image (.pdi/.bit), processor boot image (.bin) |
Programming file (generated by programming file generator, part of the Quartus Prime programmer) | The programming file to be deployed on the device after concatenating firmware, software, and the PL bitstream |
| Tool to program the hardware logic and debug the design running on the logic | Hardware manager | System console | Both enable programming the hardware logic and debugging the design running on the logic |
| Computation accelerators | AI Engines (SoC) and DSP Engines (PL) | DSPs (FPGA) includes the AI Tensor block | IP processing elements used for DSP, AI, and machine learning |