Minor recoding might be needed in the HDL portion where an IP core was inferred to ensure efficient realization in the converted design. Pay attention to the information and warning messages in the synthesis log file. As part of the conversion process, it can be easier to individually synthesize each module containing inferred IP cores because this provides easier readability of the log file (less clutter) and quicker turn-around time when debugging. After each module's synthesis log is clean, you can take the entire design through the flow.
An example of a synthesis log file is shown in the following figure. The design synthesized in this example contains only a single-port RAM HDL template, 8-bits wide and 128-bits deep. The log shows a RAMB18 being inferred from the template, along with an informational message that it might be more efficient to implement this RAM as a LUT RAM.