SoC Architecture Comparison

Processing System: Peripherals Comparison

The following tables provide a high-level comparison of the SoC architectures, covering aspects such as the processing system, memory subsystems, and other integrated low- and high-speed interfaces. Understanding these differences can aid you in targeting the best device for your migration. In instances where extra care must be taken are highlighted, such as managing on-chip memory capacity. Refer to the following documents for further details:

Zynq UltraScale+ MPSoC Data Sheet: Overview (DS891)
Zynq UltraScale+ Device Technical Reference Manual (UG1085)
Agilex 3 FPGAs and SoCs Device Overview (ID: 817231)
Hard Processor System Technical Reference Manual: Agilex 5 SoCs (ID: 814346)
Versal Adaptive SoC Technical Reference Manual (AM011)
Versal Architecture and Product Data Sheet: Overview (DS950)

Table 1. Zynq UltraScale+ MPSoC PS vs Agilex 3C HPS: Processors
	Zynq UltraScale+ MPSoC		Agilex 3C (A3C100/A3C135)
Processor core	Quad-core Arm Cortex-A53	Dual-core Arm Cortex-R5F	Dual-core Arm Cortex-A55
Processor extensions	Arm Neon™ architecture extension and single/double precision floating point		Neon and single/double precision floating point
Maximum frequency	1.5 GHz	600 MHz	0.8 GHz (Cortex-A55)
L1 cache	32 KB instruction, 32 KB data per core	32 KB instruction, 32 KB data per core	32 KB instruction, 32 KB data per core
L2 cache	1 MB 16-way set-associative level 2 cache with ECC (shared among CPUs)		128 KB
GPU	Arm Mali-400 MP2 up to 667 MHz

Table 2. Zynq UltraScale+ MPSoC PS vs Agilex 3C HPS: Peripherals
	Zynq UltraScale+ MPSoC	Agilex 3C (A3C100/A3C135)
On-chip memory	256 KB with ECC	512 KB
External memory support	DDR4, DDR3, DDR3L, LPDDR4, LPDDR3	LPDDR4
External static memory support	2x Quad-SPI, NAND, NOR	NAND x1, SDMMC x1
DMA channels	16 (2 controllers with 8 channels each)	8
Peripherals	2x UART, 2x CAN 2.0B, 2x I2C, 2x SPI, 4x 32b GPIO	UART x2, I3Cx2, I2C x5, SPIx4, 2x 24b GPIO
Security	RSA authentication, AES and SHA-3/384 decryption for FSBL, bitstreams, and other modules	RSA authentication, AES ENC, DEC, ECDSA authentication
Display port	Up to 2 lanes @ 5.4 Gb/s

Table 3. Zynq UltraScale+ MPSoC PS vs Agilex 5 HPS: Main Peripherals
	Zynq UltraScale+ MPSoC	Agilex 5
PS USB	2x USB 3.0 at 5 Gb/s 2x USB 2.0 DRD 480 Mb/s	1x USB 3.1 Gen 1 5 Gb/s 1x USB 2.0 OTG 480 Mb/s
PS PCIe®	Gen2x4	–
SATA	3.1 at 6 Gb/s	–
PS Ethernet	1 GbE x1 (SGMII support)	TSN: at 1 Gb/s (via pins) TSN: at 2.5/1 Gb/s (via fabric) x3
Display Port	Up to 2 lanes at 5.4 Gb/s	–
DDR	(LP)DDR4 – 2400 Mb/s	Up to 2x (LP)DDR5 – 4267 Mb/s
Display port	Up to 2 lanes at 5.4 Gb/s	–
Peripherals w/built-in DMA	2x USB 3.0, 4x tri-speed gigabit Ethernet, 2x SD/SDIO	USB 3.1 x1, USB 2.0 OTG x1, Gigabit Ethernet x3, SD/SDIO x1, NAND controller x1
Security	Configuration security unit (CSU)	Secure device manager (SDM)

Table 4. Versal Device Cortex-A72 Based PS vs Agilex 5 HPS: Processors
	Versal Device Cortex-A72 Based PS		Agilex 5
Processor core	Dual-core Arm Cortex-A72	Dual-core Arm Cortex-R5F	Dual-core Arm Cortex-76	Dual-core Arm Cortex-A55
Processor extensions	Neon and single/double precision floating point		Neon and single/double precision floating point	Neon and single/double precision floating point
Maximum frequency	1.7 GHz	0.8 GHz	1.8 GHz	1.5 GHz
L1 cache	48 KB instruction, 32 KB data per core w/parity and ECC	32 KB instruction, 32 KB data per core	64 KB instruction, 64 KB data per core	32 KB instruction, 32 KB data per core
L2 cache	1 MB L2 cache with ECC		256 KB L2 cache per core	128 KB L2 cache per core
L3 cache			Total 2M L3 lockable shared with 4 cores

Table 5. Versal Device Cortex-A72 Based PS vs Agilex 5 HPS: Peripherals
	Versal Device Cortex-A72 Based PS	Agilex 5
On-chip memory	256 KB with ECC	512 KB
External memory support	Up to 4 controllers LPDDR4–4267 Mb/s DDR4–3200 Mb/s	Up to 2 controllers (LP)DDR4/5–4267 Mb/s
External static memory support	OSPI, QSPI, Emmc 4.51, SD 3.0	QSPI, Emmc 5.1, SD 6.1, ONFI v1.x, 2.x
DMA channels	2 controllers with 8 channels each	2 controllers with 8 channels each
Peripherals		UART x2, I3C x2, I2C x5, SPI x4, 2x 24b GPIO
Security	Platform management controller (PMC)	Secure device manager (SDM)

Table 6. Versal Device Cortex-A72 Based PS vs Agilex 5 HPS: Main Peripherals
	Versal Device Cortex-A72 Based PS	Agilex 5
PS USB	2x USB 2.0 DRD at 480 Mb/s	1x USB 3.1 at 5 Gb/s 2x USB 2.0 OTG at 480 Mb/s
PS Ethernet	2x 1 GbE	TSN at 1 Gb/s (via pins) TSN at 2.5/1 Gb/s (via fabric) x3
DDR	Up to 4 controllers LPDDR4–4267 Mb/s DDR4–3200 Mb/s	Up to 2 controllers (LP)DDR4/5–4267 Mb/s

SoC Architecture Comparison - UG1192

AMD Design Conversion for Altera FPGAs and SoCs Methodology Guide (UG1192)

Processing System: Peripherals Comparison