The AMD Vivado™ Design Suite offers the most comprehensive solution for simulation in the FPGA/SoC industry. All of the Vivado Design Suite editions (including free Standard Edition) come with an integrated full-featured mixed language simulator to address your verification needs. The Vivado simulator has no line or instance limitations. In addition, Vivado tools support the following third-party simulators for both integrated (pushbutton flow) and script-based flow:
- Siemens® EDA QuestaSim or ModelSim
- Cadence® Incisive Enterprise Simulator (IES)
- Synopsys® VCS®
- Aldec® Active-HDL™ or Riviera-PRO™