The following table shows the revision history for this document.
| Section | Revision Summary |
|---|---|
| 7/15/2025 Version 3.0.1 | |
| kdt1738555332348.html | Updated title. |
| 6/18/2025 Version 3.0 | |
| General updates | Replaced older information throughout document with updated data and references. |
| 2/09/2018 Version 2.2 | |
| General updates | Updated Table 1-1. Removed obsolete video links for Customizing and Instantiating IP, Programming and Debugging Design in Hardware, Inserting Debug Cores into the Design, and Debugging Remotely Using Vivado. |
| 5/12/2017 Version 2.1 | |
| General updates | Added Spartan 7 FPGA and Zynq 7000 SoC single-core information throughout document. Added note to Table 2-2. |
| 11/25/2015 Version 2.0 | |
| General updates | Added Zynq 7000 SoC, Artix 7 FPGA, Cyclone V FPGA, and Cyclone V SoC FPGA information to Chapter 2, Architecture Analysis. Added Chapter 4, SoC Conversion. Reformatted Chapter 6, RTL Conversion and added a Recommendation following Figure 6-1. |
| 9/30/2015 Version 1.0 | |
| Initial release. | N/A |