Review of Altera SDC File - UG1192

Typically, an SDC file for an Altera design includes constraints for:

• Primary clock constraints with the create_clock constraint.
• Propagated clock constraints with a create_generated_clock constraint.
• Device input and output delay constraints: set_input_delay and set_output_delay.
• User clock uncertainty constraints (if any) with the set_clock_uncertainty constraint.
• derive_pll_clocks command for MMCM/PLL generated clocks.
• derive_clock_uncertainty command for interclock and intraclock uncertainty constraints.
• Clock domain crossing constraints such as set_clock_groups, set_max_skew, and set_date_delay command.
• Other exception constraints, such as set_max_delay, set_multicycle_path and set_false_path commands.

Vivado synthesis uses different naming and hierarchy rules compared to Quartus. In most cases, the SDC commands from a Quartus design need modifications to match the Vivado hierarchical cell, net, or pin naming.