Resource Utilization

The verification of the post-synthesis resource utilization is the key to correct design conversion. It can be difficult to compare the resource utilization of the converted complex IP to the original IP. However, the resource utilization of the inferred logic in Quartus and Vivado tools needs to be comparable. First, compare the top-level utilization metrics (see the following table). A detailed hierarchical comparison could be needed based on the initial comparison result.

Table 1. Sample Utilization Comparison Table
	Synthesis Resource Estimate
	Logic LUTs	Memory LUTs	Total LUTs	FFs	M20K/ RAMB18	RAMB36	DSPs
Quartus		N/A			N/A
Vivado
	Implementation Resource Utilization
Quartus
Vivado

Use the following terms as a guide, extract the resource utilization from the reports generated by the tools to populate the table.

Quartus: Utilization figures can be gathered from these locations:
- Analysis and synthesis – Resource Usage Summary report
  - Logic LUTs = total LUTs: Combinational ALUT Usage for Logic
  - FFs: Dedicated Logic Registers
  - DSP: Total DSP Blocks
- Fitter – Resource Usage Summary report
  - Logic LUTs: Combinational ALUT Usage for Logic
  - Mem LUTs: Memory ALUT Usage
  - Total LUTs: Logic LUTs + Mem LUTs
  - FFs: Dedicated Logic Registers
  - RAMB18/M20K: M20K Blocks
  - DSP: Total DSP Blocks
- Vivado synth_design – Utilization report
  - Logic LUTs: LUT as Logic
  - Mem LUTs: LUT as Memory
  - Total LUTs: Slice LUTs
  - FFs: Slice Registers
  - DSP: DSPs
  - RAMB18: RAMB18
  - RAMB36: RAMB38/FIFO

Note: The synth_design utilization report does not include any out-of-context (OOC) IP utilization figures. To circumvent this difference, either set the synthesis options for IP to global or regenerate the utilization report (report_utilization) from the synthesized design view.

When the table is populated, utilization anomalies are highlighted and some potential causes are listed:

Logic LUTs/registers:
- IP, otherwise hierarchical utilization comparisons are required.
- Asynchronous resets: AMD DSPs, SRLs, and block RAMs do not support asynchronous resets.
- Unrecognized RAM templates that can cause RAMs inferred as large register-arrays.
Mem LUTs + RAMB18/M20K+RAMB36
- Data-width: for 20-bit wide RAMs, RAMB36 are required.
- Difference in inference threshold between distributed RAM versus block RAM.
- Unrecognized RAM templates that can cause RAMs inferred as large register-arrays.

A detailed report of all memories in the design can be generated using the report_ram_utilization report. Review memories with low bit utilization and question if large arrays of RAMB36 cannot be remapped to the larger URAM288 which can replace eight such primitives.

Hierarchical utilization reports are generated by setting the -flatten_hierarchy none option for Vivado synthesis. Retaining hierarchy prevents cross-boundary optimization and can generate a sub-optimal netlist. Consequently, after completing the comparison, reset the setting to the default -flatten_hierarchy rebuilt to generate an optimized netlist.

Recommended: AMD recommends exporting the reports to a *.CSV file format. The *.CSV files can be imported into spreadsheets and can be easily compared, or can be merged together for more advanced comparison.

To gather the hierarchical utilization report from Quartus Prime, export the Resource Utilization by Entity by right-clicking on the report in the Compilation Report – Fitter section. It is not recommended to use the resource utilization report from analysis & synthesis because it is less detailed and misses information (that is, memories).

A hierarchical utilization report is not available by default in the Vivado Design Suite, but it can be generated by opening the synthesized design and issuing this command:

report_utilization -hierarchical -file <filename>

Resource Utilization - UG1192

AMD Design Conversion for Altera FPGAs and SoCs Methodology Guide (UG1192)