Replacing AMD Primitives - UG1192

AMD Design Conversion for Altera FPGAs and SoCs Methodology Guide (UG1192)
Document ID
UG1192
Release Date
2025-07-15
Revision
3.0.1 English

When migrating a design, you must convert common Altera primitives to the AMD FPGA equivalents. Primitives are the basic building blocks of an AMD design. Primitives perform dedicated functions in the device and implement standards for I/O pins in AMD devices. The following table shows a subset of I/O primitives available in AMD devices.

Table 1. AMD I/O Primitive Mapping
Description AMD Primitive Altera Equivalent Conversion Method
Single input buffer IBUF Wire/signal assignment HDL
Single output buffer OBUF Wire/signal assignment HDL
Global clock buffer BUFG Wire/signal and global signal assignment HDL and assignment editor
Input buffer with selectable interface IBUF_<selectable I/O standard> Wire/signal and I/O standard assignment  
Bidirectional buffer with selectable interface IOBUF_<selectable I/O standard> Wire/signal and I/O standard assignment  

Output buffer with selectable interface

 OBUF_<selectable I/O standard> Wire/signal and I/O standard assignment  
Differential I/O buffer IBUFDS, OBUFDS Wire/signal and I/O standard assignment  
16-bit shift register SRL16 AUTO_SHIFT_REGISTER_RECOGNITION Assignment editor

For additional details on I/O replacing AMD primitives refer to Primitive Elements and I/O in RTL conversion.