When none of the previous methods are feasible, the generated Vivado IP core can be made parameterizable. Typically, this flow is used for FIFOs and memories with ECC. For example, to add parameterization to a Vivado Design Suite-generated block memory, as shown in the following figure.
Figure 1. Adding Parameterization to a Vivado Design Suite-Generated Block Memory
Important: This flow must be applied with
great care: 1. Parameter values are not verified during synthesis, only during IP
generation. 2. Constraints files (that is, FIFO) depend on the IP configuration – only use
limited parameterization.
This process involves generating the IP core from the Vivado IP catalog and then editing the IP core files. This process is described step-by-step in article 57546.
By referencing the AMD core instance (XCI) file (recommended), you have access to the IP core source files for simulation and synthesis, as well as for implementation.