Replace Parameterizable IP With Static IP Core - UG1192

AMD Design Conversion for Altera FPGAs and SoCs Methodology Guide (UG1192)

Document ID
UG1192
Release Date
2025-07-15
Revision
3.0.1 English

Use this flow when there are only a few variants of a specific IP core file used in your design.

  1. Generate several static IP cores with the Vivado IP catalog to cover all variants.
  2. Use generate statements to conditionally instantiate the corresponding Vivado IP core.

This is an example of the content of the wrapper that conditionally instantiates the correct configurations of the RAM:

entity RAM_A is
 generic (DATAWIDTH: integer := 8);
 port (...);
end RAM_A;
architecture RTL of RAM_A is
begin
 8_BIT: if DATAWIDTH=8 generate
 RAM_A8_i: entity work.RAM_A8
 port map
 (...);
 end generate 8_BIT;
 16_BIT: if DATAWIDTH=16 generate
 RAM_A16_i: entity work.RAM_A16
 port map
 (...);
 end generate 16_BIT;

Typically, this method is used for FIFOs and memories with ECC, which cannot be inferred.