Replace Parameterizable IP With Inferred IP - UG1192

AMD Design Conversion for Altera FPGAs and SoCs Methodology Guide (UG1192)

Document ID
UG1192
Release Date
2025-07-15
Revision
3.0.1 English

Whenever possible, write HDL to infer memories and DSP functions. Inferring offers many advantages, such as architecture independence, full parameterization, and lowest simulation runtime.

Inferable code examples are available in the Vivado Design Suite language templates. These templates are for non-parameterizable code, however parameterization can be added if required.