Within the device design, there are multiple ways to specify the clock signals that need to access the global clock resources. When using MMCMs, PLLs, XPLLs, and DPLLs, the recommended method of instantiation is to use the Clocking Wizard. In Vivado tools, the clocking wizard IP dialog box can guide instantiation of MMCMs and PLLs along with any needed clock buffers attached to them. See the Clocking Wizard LogiCORE IP Product Guide (PG065) for UltraScale devices or the Clocking Wizard for Versal Adaptive SoC LogiCORE IP Product Guide (PG321). The Clock Features tab shown in the following figure includes the clock management type (green square) and whether the clocking wizard instantiates a BUFG (red square, where all options other than No buffer instantiates a BUFG).
In the Output Clocks tab, all options other than No_buffer in the Drives column instantiates a clock buffer on the output of the clocking wizard (shown with a red square in the following figure). On Versal device designs, some buffers can be combined when an MBUFG is determined to be the best solution. Buffer and Buffer with CE are usually preferred because these options allow the clocking wizard to choose the optimal clock management primitive, for example, instantiating an MBUFG to drive multiple outputs on a Versal device, if the clock output characteristics allow it. See the Auto Buffer Selection and Clock Grouping section in Clocking Wizard for Versal Adaptive SoC LogiCORE IP Product Guide (PG321) or the Auto Buffer Selection in Clocking Wizard LogiCORE IP Product Guide (PG065). UltraScale devices also require the Optimize Clocking Structure checkbox to be used to obtain the best clock structure with the Buffer selections.
If there is a need for clock buffers other than those instantiated by the clock wizards a few methods can be used. Simple clock buffers such as BUFG can be added to net objects using the CLOCK_BUFFER_TYPE property. For IP integrator designs a Utility Buffer IP can be instantiated for all global clock buffer types. For all other use cases, the clock section in UltraScale Architecture Libraries Guide (UG974) provides the templates to instantiate clock primitives in the RTL. The Vivado tools can also infer global clock buffers when used as a clock for a register in the RTL, if clock resources are available. An input buffer might be needed if instantiating a global clock that needs special I/O features for example, for differential signaling use the IBUFDS. The instantiation template for these input buffers can be found in the I/O section of the libraries guide for the device family.