This section covers the different aspects of converting low-level IP cores, such as RAMs, FIFOs, clocking, adders, multipliers, and shift-registers. In general, using low-level IP cores are associated with RTL-based designs. IP Core Conversion describes higher-level design flows or interfaces.
Inferred Logic
In general, synthesizable HDL code written in Verilog or VHDL for use with Quartus Prime is compatible with the AMD Vivado design tools without modification. The RTL code might have additional synthesis pragmas to guide the Altera synthesis tools to behave in a certain manner. These pragmas probably need to be translated into the corresponding Vivado Design Suite equivalent. Synthesis and Implementation provides a mapping of these pragmas.
HDL code can be inferred as an IP core. Both Altera and AMD provide HDL templates for inferring IP cores. These templates are example segments of HDL code that are designed so that the synthesis tool recognizes a low-level IP function and implements it appropriately. There might be minor variants in some of the Quartus Prime core templates versus the corresponding Vivado IP templates.
You need to inventory (as explained in the Altera Quartus Prime IP Cores section) the existing IP cores in your design and ensure that each IP core instance is translated properly. The Quartus Prime log file lists inferred IP cores in the LPM parameter settings section of the compilation report.
Vivado Language Templates
See the Vivado Design Suite User Guide: Synthesis (UG901) HDL Coding Techniques section for further information about inferring IP blocks using HDL templates.