Early clock infrastructure testing can be done using Vivado tools, if a full design is not ready. This is a part of the I/O and Clock Planning Design Flow. A few extra suggestions not included in the design flow are listed here.
- Create a clock diagram. Use a program like Microsoft Visio.
- Follow the Altera to AMD Clock Conversion Process using a skeleton
of a design. A few recommendations on the first design:
- A pinout design in the Vivado tools can be a starting point for a skeleton design (if available) and migrated to an RTL project (see Vivado Design Suite User Guide: I/O and Clock Planning (UG899)).
- Each clock must be connected to synchronous primitives. They can be in IP or you can use a placeholder. This is to preserve clock primitives and not have them removed during optimization.
- The synchronous primitives must have their datapath connected to the integrated or embedded blocks or I/O. This is to preserve the clock primitives and not have them removed during optimization.
- Check the design using report_drc and report_ssn post-synthesis to validate that the clock infrastructure is valid.
- Check the design post-implementation using report_clock_utilization, report_drc, and report_route_status.
- Further debug and reporting information can be found in the Clocking Visualization, Report Generation, and Debug section.