In Project Mode, the Vivado Design Suite manages the design process, including dependency management, report generation, and data storage. It uses a directory structure to organize and update design source files and tracks synthesis and implementation runs. Key advantages include:
- Automatic management of the entire design flow
- Prompting for re-synthesis or re-implementation when changes are made.
- Automatic generation of timing, DRC, methodology, and power reports after routing
- Single-click execution of the full design flow within the IDE
The following image is a GUI overview and includes the project mode flow.
Figure 1.
Vivado IDE Viewing Environment
- The
Vivado flow
navigator is an essential part of the Vivado Design Suite. It serves as the central point of navigation for
different stages of FPGA or adaptive SoC design, offering easy access to workflows
and tools.
- Advantages of the flow navigator
-
- Ease of use
- Streamlines complex FPGA design workflows by organizing them into logical steps.
- Quick access
- Reduces the need to navigate multiple menus, enabling faster transitions between design phases.
- Guided flow
- Ensures users follow the correct order of operations, minimizing errors and inefficiencies.
In essence, the flow navigator is the roadmap for moving through the Vivado design process—from design entry to implementation, and finally, programming the FPGA.
Key features of the flow navigator are listed in 2 – 8.
- Project manager: Show project manager actions. Switch to the project manager
environment.
- Settings
- Allows access to project and tool settings.
- Add sources
- Create or add source files (RTL, constraints, IP) to add to the project.
- Language templates
- Display the language templates window.
- IP catalog
- Browse, customize, and generate IP from the IP catalog.
-
IP integrator: Show IP integrator
actions. Switch to the IP integrator environment.
- Create block design
- Create and add an IP subsystem to the project.
- Open block design
- Open an IP subsystem from the current project.
- Generate block design
- Generate outputs needed for synthesis, simulation, and implementation.
- Export platform
- Export a hardware description file for use with the Vitis tools.
- Simulation: Show simulation actions. Switch to the simulation environment.
- Run simulation
- Launch Vivado simulator.
- RTL analysis: Show RTL analysis actions. Switch to the RTL analysis
environment.
- Run linter
- Analyze the RTL design code, providing a detailed report for any violations.
- Open elaborated design
- Analyze and constrain an elaborated netlist.
- Synthesis: Show synthesis actions. Switch to the synthesis environment.
- Run synthesis
- Run synthesis on the project source files.
- Open synthesized design
- Analyze and constrain a post synthesis netlist.
- Implementation: Show Implementation actions. Switch to the implementation
environment.
- Run implementation
- Implement the active synthesized netlist.
- Open implemented design
- Analyze and constrain an implemented design.
- Program and debug: Show program and debug actions. Switch to the program and
debug environment.
- Generate bitstream
- Generate a programming file after implementation.
- Open hardware manager
- Open the hardware program and debug manager.
- Hierarchical sources window: Allows to manage project source files (HDL, IP
cores, constraint files, simulation, etc.) including adding, removing, and
reordering the sources to meet specific design requirements.
- Design sources
- Displays source file types, including SystemVerilog, Verilog, VHDL, IP cores, digital signal processing (DSP) modules, and block designs.
- Constraints
- Displays constraint files, which are assigned to constraint sets.
- Simulation sources
- Displays the source files that are used for simulation.
- Sources window views
- Displays the following views
- Hierarchy
- Displays the hierarchy of the design modules and instances, along with the source files that contain them.
- IP sources
- Displays all the files defined by an IP core.
- Libraries
- Displays the sources sorted into the various libraries. Can be used to create new libraries and manage files.
- Compile order
- Displays source files in the order in the files are compiled, from first to last, and shows the processing order for constraints.
- Properties window: Dynamically displays information/properties of the selected object in the Vivado Integrated Design Environment (IDE).
- Project summary: An interactive project summary that updates dynamically as
design commands are run and the design progresses through the design flow.
- Overview
- Provides project and design information, such as the project settings, part, board, and state of synthesis and implementation. It also provides links to detailed information, such as links to the messages and reports windows as well as the settings dialog box. As synthesis and implementation complete, DRC violations, timing values, utilization, and power.
- Dashboard
- Can be configured to view and analyze data in either tabular or graphical form and compare values across multiple runs.
- Tool/design information window: Dynamic area that displays design information.
- Tcl console
- Central control and display of low-level Tcl commands. Displays messages from previously executed Tcl commands, command errors, warnings, and successful completion. Status of design loads and reading constraints.
- Messages window
- Displays design and report messages with a link to the relevant object or source file, which are grouped to enable to locate messages from different tools or processes.
- Log window
- Displays in a continuous scrollable format and is overwritten when new commands are run. The active output status of commands that compile the design such as synthesis, implementation, and simulation.
- Reports window
- Displays reports for the active run and updates as various steps are complete. Reports are grouped under headings named after the different steps to enable quick location of information.
- Design runs window
- Design runs window to view, configure, launch, reset, and analyze synthesis and implementation runs.
- Find results, package pins, I/O ports, and timing summary windows
- These windows as well as various reports appear in this area as needed.