For power estimation, AMD supports two different tools based device families supported. The Xilinx Power Estimator (XPE) and Power Design Manager (PDM) tools can provide reliable data based on defining your resource utilization. Additionally, thermal models are available in Siemens Flotherm and Ansys IcePAK formats. Both tools and thermal models are available at AMD Power Efficiency.
The 7 series and UltraScale devices use the XPE tool, a spreadsheet-based tool that provides power consumption estimation broken out by device resource and voltage rails. The XPE tool also allows you to specify thermal impedance targets in the environmental input section to assist in the design of thermal solutions. The XPE tool shows reasonable design targets that are used to calculate how much power you can realistically draw while staying within your thermal budget. See Xilinx Power Estimator User Guide (UG440).
For Versal and UltraScale+ devices, the PDM tool is used not only for power estimation but also for design specific decoupling recommendations. The PDM tool is the next generation tool for AMD that incorporates all the tools available in XPE, while adding more capabilities in a GUI based tool. For details on using the PDM tool see the Power Design Manager User Guide (UG1556).
Both the XPE and PDM tools also support importing data from the Vivado Design Suite for the most accurate power estimations. The Vivado tool has a Report Power function that outputs a file to import into either of the estimation tools to provide the most realistic resource utilization and power modeling. The limitation of the report power function is that the logic design must be complete before the report provides meaningful data. The report power function can also be used as a design verification tool after the design is complete to compare the results to the pre-design estimations.
In addition to the XPE and PDM tools, AMD provides a power and thermal checklist (AR000034125) to help eliminate any potential issues with power and thermal early in the design cycle.