Parameterizable Altera IP are IP cores that can represent a different configuration through Verilog parameters or VHDL generics.
For example:
- A RAM IP core instantiated in Verilog used multiple times with different data width, parameterized through a Verilog parameter.
- A VHDL FIFO IP core used multiple times with a different depth, configured through a VHDL generic.
When generated from the Quartus Prime IP catalog and IP Parameter Editor, Quartus IP cores are not parameterizable – their configuration is static based on the settings specified in the Quartus Prime IP Parameter Editor. However, it is not uncommon for RAMs, FIFOs, and DSP functions to reuse the same IP core multiple times with different configurations through parameters of generics. Altera also provides a library of parameterized modules (LPM).
Flow
The first step in converting these parameterizable IP cores is to identify all configurations. The Analysis section showed how to find all configurations present in the design and build up a list. When there are parameterizable IP core in a design, AMD recommends adding the IP core parameters to this list. The conversion of parameterizable IP core depends on the amount of variants of an IP core. Consider both short-term effort and long-term portability needs as you choose from one of the options described in this section: