The ports connecting the PS and PL (referred to as HPS and FPGA in Altera terminology) are similar to those in the Zynq UltraScale+ MPSoC and Versal devices with Cortex-A72 based PS, but with some differences. AMD devices include general-purpose AXI ports, high-performance AXI ports, and an accelerator coherency port (ACP), among others differences. Altera devices use the FPGA-to-SDRAM interface, FPGA-to-HPS bridge, HPS-to-FPGA bridge, and the lightweight HPS-to-FPGA bridge. See the following tables.
| HPS ↔ Fabric | Agilex 5 | Equivalent Zynq UltraScale+ MPSoC | Designing to Manage the Differences |
|---|---|---|---|
| FPGA-to-SDRAM bridge (F2SDRAM) | 1x 256-bit AXI4 fabric access to DDR memory Lower latency than F2SOC support Non-coherent with the HPS |
4x 128-bit PL to PS-FPD | Improved throughput: The four 128-bit paths can be used in parallel to achieve higher throughput compared to a single 256-bit path. This can be managed by distributing the data across the four paths, ensuring balanced load and avoiding bottlenecks. |
| FPGA-to-HPS bridge (F2H or F2SOC) | 1x 256-bit ACE-Lite5 fabric access to
DDR, OCRAM, and HPS peripherals Coherent and non-coherent transactions Cache stashing into L1, L2, and L3 caches |
4x 128-bit PL to PS-FPD (HPC ports) 128-bit AXI PL to PS-LPD for OCM and PS peripherals 128-bit ACP exclusively for L2 cache |
Coherency management: Use the multiple 128-bit paths to separate coherent and non-coherent transactions, reducing contention and improving performance. Cache stashing can be managed by directing specific transactions to the ACP for L2 cache. |
| HPS-FPGA bridge (H2F) | 1x 128-bit AXI4 port from HPS to fabric for high bandwidth access | 128-bit AXI4 PS-LPD to PL and 2x 128-bit PS-FPD to PL for non-coherent and coherent transactions | Bandwidth optimization: Use the multiple 128-bit paths to segregate high-bandwidth and low-latency transactions, ensuring efficient data transfer and reducing the risk of congestion. |
| Lightweight HPS-to-FPGA bridge (LWH2F) | 1x 32-bit AXI4 port from HPS to fabric for low bandwidth access to soft IP control and status registers | 128-bit AXI4 PS-LPD to PL | |
| Peripheral fabric ports | Using fabric, I/Os for HPS peripherals | EMIO | |
| Not available | 128-bit ACE from PL to PS for fully coherent transactions |
Additional AXI4 resource: PL master with cache coherent transactions |
| HPS ↔ Fabric | Agilex 5 | Equivalent Versal Device Cortex-A72 Based PS | Designing to Manage the Differences |
|---|---|---|---|
| FPGA-to-SDRAM bridge (F2SDRAM) | 1x 256-bit AXI4 fabric access to DDR memory Lower latency than F2SOC support Non-coherent with the HPS |
NoC for DDR memory |
The NoC-based memory access in Versal devices provide better scalability and efficiency compared to direct AXI4 connections. It helps optimize bandwidth across multiple masters without congestion issues (programmable connectivity/NoC QOS settings) |
| FPGA-to-HPS bridge (F2H or F2SOC) | 1x 256-bit ACE-Lite5 fabric access to DDR memory, OCRAM, and HPS
peripherals Coherent and non-coherent transactions Cache stashing into L1, L2, and L3 caches |
NoC for DDR memory 128-bit AXI4 PL to PS-LPD for OCM and PS peripherals 128-bit ACP exclusively for L2 cache |
NoC-based access provides better routing and scalability compared to direct fabric-based access. Ability to separate coherent and non-coherent transactions |
| HPS-FPGA bridge (H2F) | 1x 128-bit AXI4 port from HPS to fabric for high-bandwidth access | 128-bit AXI4 PS-LPD to PL and PS-FPD to PL for non-coherent and coherent transactions |
Versal devices provide both coherent and non-coherent access paths. Coherent transactions to reduce redundant memory operations. |
| Lightweight HPS-to-FPGA bridge (LWH2F) | 1x 32-bit AXI4 port from HPS to fabric for low bandwidth access to soft IP control and status registers | 128-bit AXI4 PS-LPD to PL | Versal devices provide much higher bandwidth compared to Agilex |
| Peripheral fabric ports | Using fabric, I/Os for HPS peripherals | EMIO | |
| Not available | 512-bit ACE from PL to PS for fully coherent transactions |
Additional AXI4 resource |