Other DSP IP and Reference Designs - UG1192

AMD Design Conversion for Altera FPGAs and SoCs Methodology Guide (UG1192)

Document ID
UG1192
Release Date
2025-07-15
Revision
3.0.1 English

This section included a brief introduction into the wide array of signal processing capabilities of which AMD has long been the industry leader. The following list includes additional signal processing algorithms which constitute only a subset of the possibilities provided by AMD.

This list only includes IP provided by AMD. There is a larger searchable catalog of AMD and third party IP to help speed up development. There are also examples for DSP designs in the Vitis tools model composer for AIE and/or PL found in examples and tutorials on GitHub. If HLS is the preferred design entry method, there are HLS DSP libraries.

Further DSP Hardware

Exciting new capabilities are being introduced with the SoC variants of the adaptive computing devices. This includes dedicated sampling interfaces with the Zynq UltraScale+ RFSoC, numerous integrated IPs which address common signal processing applications (example, DFE), and AI Engines that are a new and exciting silicon construct for the realization of DSP algorithms.