Non-project Mode - UG1192

AMD Design Conversion for Altera FPGAs and SoCs Methodology Guide (UG1192)

Document ID
UG1192
Release Date
2025-07-15
Revision
3.0.1 English

Non-project mode in the Vivado Design Suite allows you to work without the overhead of managing a Vivado project. Instead of relying on the IDE to track the state of the design, you use Tcl scripts and commands to drive the entire design flow. This mode is particularly advantageous for automated and repetitive tasks, as it provides a streamlined environment, free from the constraints of the graphical interface.

In Non-Project Mode, you manage design sources and the design process yourself using Tcl commands or scripts. The key advantage is that you have full control over each step of the flow. For example:

  • If you modify an HDL file after synthesis, you must remember to rerun synthesis to update the in-memory netlist.
  • If you want a timing report after routing, you must explicitly generate the timing report when routing completes.
  • Design parameters and implementation options are set using Tcl commands and parameters.
  • Design checkpoints can be saved and reports created at any stage of the design process using Tcl commands.

As the design flow progresses, the representation of the design is retained in memory in the Vivado Design Suite. Non-project mode discards the in-memory design after each session and only writes data to disk that you instruct it to.