All Versal adaptive SoCs have a programmable network on chip (NoC). This high-speed communication subsystem transfers data between intellectual property (IP) Endpoints in the programmable logic (PL), processing system (PS), and other integrated blocks, providing unified intra-device connectivity. The NoC master and slave interfaces can be configured as AXI3, AXI4, or AXI4-Stream. The NoC converts these AXI interfaces to a 128-bit wide NoC packet protocol that moves data horizontally and vertically across the device via the horizontal NoC (HNoC) and vertical NoC (VNoC) respectively. The HNoC runs at the bottom and top of the Versal adaptive SoC, close to the I/O banks and integrated blocks (for example, processors, memory controllers, and PCIe). The number of VNoCs (up to eight VNoCs) depends on the device and the amount of DDR memory controllers (up to four DDR memory controllers).
Because the NoC is integrated in the silicon, it is power-efficient and consumes no programmable logic resources. The NoC becomes operational almost immediately after power-up, requiring only minimal routing configuration. It supports terabytes-per-second data transfers via multiple 128-bit wide links that connect memories, high-speed peripherals, accelerators, and processing nodes within the device. These software-programmable, fixed, but steerable, paths remove the need for place and route. Each path within the network can have its own bandwidth and traffic class specification, enabling users to ensure that data gets to where it is supposed to at the right time.
The main function of the NoC is to efficiently move data between the DDR memory controllers and the rest of the device. The Versal adaptive SoC NoC IP enables multiple masters to access a shared DDR memory controller with advanced quality of service (QoS) settings. The AXI NoC IP is required to connect the PS or the PL to the DDR memory controller. The AXI NoC IP can also be used to create additional connections between the PS and the PL or between design modules located in the PL.
To better understand the system-level benefits of the Versal architecture's programmable NoC versus Altera, AMD recommends that developers read Optimize Design Efficiency with the Versal Adaptive SoC Programmable Network on Chip (WP562).
Tutorials and Training
The Versal adaptive SoC NoC IP is a logical representation of the Versal adaptive SoC NoC. This IP can be instantiated in the design using IP integrator or an RTL XPM. Refer to the Vivado tools language templates for examples of the XPM.
For more information on the NoC IP and performance, see the Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313).