The delay through board traces is not fixed due to the changing physical environment of the board. Consequently, a calibration step is required for the memory controller (on the FPGA) to be able to exchange data reliably with the external memory.
While Altera offers the Altera External Memory Interface Toolkit, the AMD Memory Calibration Debug Tool allows you to debug calibration or data errors in UltraScale devices memory interfaces (DDR4/3, RLDRAM3, and QDRII+). You can always view and analyze core configuration, calibration status, and data margin of the memory interfaces for read and write at any time throughout operation in hardware.
Vivado Logic Analyzer
These AMD user guides, articles, and videos provide detailed information about the Vivado logic analyzer tool:
- To get started learning about the Vivado Design Suite, see the Vivado Design Suite User Guide: Programming and Debugging (UG908).
- For more information on what Tcl commands are available in the Vivado Design Suite, see the Vivado Design Suite Tcl Command Reference Guide (UG835).
- For more information on how to use the memory interface example design and enable the debug feature, see the Memory Interface UltraScale DDR4/DDR3 - Hardware Debug Guide (60305).
- For more information about the memory interface generator (MIG) core that is a combined pre-engineered controller and physical layer (PHY) for interfacing UltraScale architecture-based FPGAs user designs to DDR3 and DDR4 SDRAM, QDR II+ SRAM, and RLDRAM 3 devices, see the UltraScale Architecture-Based FPGAs Memory IP LogiCORE IP Product Guide (PG150).