Behavioral code examples for memory inference for VHDL or Verilog are provided in the Coding Examples section in the Synthesis Constructs section of the Language Templates.
Figure 1. XPM Template Example
For the adaptive SoCs, PS on-chip memory (OCM) contains 256 KB of RAM memory that is accessible with its 128-bit AXI interface port. The OCM also includes ECC data protection. The OCM RAM and controller provide the following features:
- 256 KB of high-speed, low-latency memory
- Optimized for RPU accesses
- 64-bit ECC with single-bit error correction and two-bit error detection
- Exclusive access requests
- Memory protection via the OCM_XMPU with system management ID (SMID) and TrustZone screening
- Error reporting and injection
See the following documents for further information:
- Using HDL Language Templates in the Vivado Design Suite User Guide: System-Level Design Entry (UG895)
- On-chip Memory in the Versal Adaptive SoC Technical Reference Manual (AM011)