The synthesis-supported language constructs for VHDL, Verilog, and SystemVerilog are roughly equivalent between the Altera Quartus Prime design tools and the AMD Vivado™ design tools. There is a small subset of Verilog features supported by Quartus Prime synthesis, but not by Vivado synthesis:
- Hierarchical path name references
- Net data types of wand, wor, triand, and trior
- Config/endconfig
The Vivado Design Suite supports many more VHDL-2008 constructs than Quartus Prime. The default type for
*.vhd files in Vivado tools is VHDL. The type either needs
to be changed in the properties window to VHDL 2008 or 2019, or can be changed through Tcl:
set_property FILE_TYPE {VHDL 2008} [get_files <file>.vhd]
SystemVerilog files with a *.v extension are handled differently in the Vivado Design Suite and Quartus Prime design tools. In Quartus Prime, there is a
global option to treat all *.v files as SystemVerilog
files. In the Vivado tools, the file_type property is set on the *.v files to
treat them as SystemVerilog files.
Unlike Quartus Prime, the Vivado synthesis tool compiles the *.v files with the Verilog 2005 syntax and the *.sv files with the SystemVerilog syntax, leading to macro (define) visibility issues between the two groups of files.